1. Field of the Invention
The present invention relates to a semiconductor device having a semiconductor integrated circuit with a resistance circuit formed on the same semiconductor substrate.
2. Description of the Related Art
In a semiconductor integrated circuit, the following types of resistors are used: a diffused resistor made from a monocrystalline silicon semiconductor substrate into which impurities of a conductivity type opposite to that of the semiconductor substrate are introduced; and a polycrystalline silicon resistor made of polycrystalline silicon into which impurities are introduced.
A sectional view in which a resistance element used for a conventional resistance circuit and an insulated gate field effect transistor (hereinafter, abbreviated to MISFET) are combined is shown in FIG. 2.
A MISFET 102 includes a thin gate oxide film 3, source and drain regions 4, and a gate electrode 5. The MISFET 102 is surrounded by a thick isolation oxide film 2. On those films, an intermediate insulating film 8 is formed, and electrical connection is achieved by metal wiring 10 via contact holes 9.
Further, a resistance element 101 is formed of a polycrystalline silicon film deposited on the flat and thick isolation oxide film 2.
In the polycrystalline silicon film forming the resistance element, there are formed high concentration impurity regions 6 at both ends of the polycrystalline silicon film and a low concentration impurity region 7 sandwiched between the high concentration impurity regions 6. The resistance value of the resistance element is determined depending on a resistivity, which is determined depending on the impurity concentration of the low concentration impurity region 7 having high resistance, and the length and the width of the low concentration impurity region 7. The high concentration impurity regions 6 are used for obtaining ohmic contact with respect to the metal wiring.
The intermediate insulating film 8 is formed on the resistance element 101, and electrical connection is achieved by the metal wiring 10 via the contact holes 9. In the resistance circuit used for the semiconductor integrated circuit, a plurality of the resistance elements of FIG. 2 are formed on the same substrate surface so as to be connected in series or in parallel to one another via the metal wiring.
The intermediate insulating film 8 formed on the MISFET 102 and the resistance element 101 contains boron or phosphorus, and is flattened through thermal treatment of 850° C. or higher. Thus, the difference in height in the semiconductor integrated circuit caused by the film patterns is reduced. Further, after the metal wiring is formed, a silicon nitride passivation film 11 is provided thereon as a protective film.
The contact holes provided in the flattened intermediate insulating film 8 as described above have depths that differ depending on the underlying structures. In the example described above, since parts of the intermediate insulating film provided on the source and the drain in the semiconductor substrate are the thickest, and a part of the intermediate insulating film provided on the resistance element is the thinnest, the contact holes for the source and the drain are the deepest, and the contact holes for the resistance element are the shallowest when the contact holes are formed in the respective parts.
When the contact holes with two depths are formed simultaneously, the contact holes for the resistance element, on which the thin intermediate insulating film is provided, are finished first, and hence until the contact holes for the source and the drain are completely made, excessive over-etching is performed on the contact holes for the resistance element. Accordingly it is necessary to set the thickness of the polycrystalline silicon film to be thick enough to prevent the contact hole from passing through the resistance element during the over-etching, or it is necessary to ensure the resistance to etching.
As a method for solving the above-mentioned problem, for example, such methods illustrated in FIGS. 3 and 4 are proposed.
In FIG. 3, in order to improve the strength to the over-etching, the contact hole 9 for connection with the metal wiring 10 is formed on a thick polycrystalline silicon film 16. Meanwhile, the resistance element main body 7 is formed of a thin polycrystalline silicon film, and the thick polycrystalline silicon film and the thin polycrystalline silicon film are connected to each other through via holes 13 provided separately from the contact hole 9 for connection with the metal wiring 10.
Further, in FIG. 4, the corresponding part to the thick polycrystalline silicon film in FIG. 3 is replaced by an impurity diffusion region 17 formed in the semiconductor substrate. Then, similar to the case of FIG. 3, the resistance element main body is formed of a thin polycrystalline silicon film, and the impurity diffusion regions and the thin polycrystalline silicon are connected to each other through via holes 13 provided separately from the contact holes 9 for connection with the metal wiring.
Such method of providing a polycrystalline silicon resistor is disclosed in, for example, Japanese Published Patent Application H09-051072.
As for manufacturing the conventional resistance element, the following problems arise.
For example, when the polycrystalline silicon resistor is employed, in order to aim for improvement in accuracy of the resistance value or increase in resistance value, the reduction of the thickness of the polycrystalline silicon film is aimed for in some cases. Particularly in recent years, along with advancement of devices and improvement in controllability of the thickness of the film to be deposited, it has become easier to realize a thin film. However, as described above, thin films have a problem of resistance to over-etching, and hence it has been difficult to utilize a resistance element formed of a thin film of 500 Å or smaller in the semiconductor integrated circuit.
In order to realize a resistance element formed of a thin film with a method other than those illustrated in FIGS. 3 and 4, there is a method of forming the resistance element by performing photomasking steps and etching steps separately for respective contacts. However, this method has a problem of causing increase in cost due to addition of the masking step. Further, when the contact holes having one depth are formed after the contact holes having another depth are formed, it is necessary to perform the photolithography process while the contact holes formed earlier are opened, which may cause contamination and adhesion of foreign matters and reduce the quality.